Digilent - Nexys A7 FPGA Trainer Board Recommended for ECE Curriculum A7-50T - 410-292-1
- Buy 3 for PKR65,075.00 each and save 5%
The Nexys A7 is the new name for our popular Nexys 4 DDR board, now available in two FPGA densities! Featuring the same Artix™-7 field programmable gate array (FPGA) from Xilinx®, the Nexys A7 is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. The Artix-7 FPGA is optimized for high-performance logic, and offers more capacity, higher performance, and more resources than earlier designs. With its large, high-capacity FPGA and collection of USB, Ethernet, and other ports, the Nexys A7 can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, a temperature sensor, MEMs digital microphone, speaker amplifier, and plenty of I/O devices allow the Nexys A7 to be used for a wide range of designs without needing any other components.
The Nexys A7-100T is compatible with Xilinx's Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. Xilinx ISE has been discontinued in favor of Vivado® Design Suite.
The Nexys A7-50T variant is compatible only with Vivado® Design Suite.
Xilinx offers free WebPACK™ versions of these toolsets, so designs can be implemented at no additional cost.
The Nexys A7 is not supported by the Digilent Adept Utility.
|Logic Slices||15,850 (4 6-input LUTs & 8 flip flops each)||8,150 (4 6-input LUTs & 8 Flip flops each)|
|Block RAM||4,860 Kbits||2,700 Kbits|
|Clock Tiles||6 (each with PLL)||5 (each with PLL)|
|Internal Clock||450 MHz+||450 MHz+|
Programming: Vivado Design Suite as well as the ISE toolset
- Xilinx Artix-7 FPGA XC7A100T-1CSG324C or XC7A50T-1CSG324C
- 15,850 logic slices, each with four 6-input LUTs and 8 flip-flops (8,150 logic slices for the A7-50T)
- 4,860 Kbits of fast block RAM (2,700 Kbits for the A7-50T)
- Six clock management tiles, each with phase-locked loop (PLL) (5 clock management tiles for the A7-50T)
- 240 DSP slices (120 DSP slices for A7-50T)
- Internal clock speeds exceeding 450 MHz
- On-chip analog-to-digital converter (XADC)
- 128 MiB DDR2
- Serial Flash
- Digilent USB-JTAG port for FPGA programming and communication
- microSD card connector
- Ships with rugged plastic case and USB cable
- USB-UART Bridge
- 10/100 Ethernet PHY
- PWM audio output
- 3-axis accelerometer
- 16 user switches
- 16 user LEDs
- Two tri-color LEDs
- PDM microphone
- Temperature sensor
- Two 4-digit 7-segment displays
- USB HID Host for mice, keyboards and memory sticks
- Pmod for XADC signals
- 12-bit VGA output
- Four Pmod ports
|Product Availability||In Stock|
|Temperature Range (Min)||NA|
|Temperature Range (Max)||NA|